{"id":36182,"date":"2022-11-17T12:23:56","date_gmt":"2022-11-17T20:23:56","guid":{"rendered":"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/?p=36182"},"modified":"2023-06-12T10:30:40","modified_gmt":"2023-06-12T17:30:40","slug":"high-speed-pcb-design-part-3-signal-integrity","status":"publish","type":"post","link":"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/high-speed-pcb-design-part-3-signal-integrity\/","title":{"rendered":"High-Speed PCB Design Part 3: Avoiding Signal Integrity Issues"},"content":{"rendered":"\n

High-speed PCB design is any design where the integrity of your signals starts to be affected by the physical characteristics of your circuit board. Part 3 of this three-part series focuses on signal integrity. What is it, and how can you avoid common issues<\/em>?<\/p>\n\n\n\n

\"high-speed-pcb-design-signal-integrity\"<\/figure>\n\n\n

What is Signal Integrity (SI)?<\/h2>\n\n\n

Signal Integrity<\/a> (SI) means the signals created at the transmitting or driving end of a circuit reach the receiving end intact enough to be used. Ideally, signals would not change on their way to the receiver because as the frequency and density of circuits increase, signals degrade, and SI becomes an issue.<\/p>\n\n\n

Factors that Affect Signal Integrity (SI)<\/h2>\n\n\n

There are several factors that affect SI. They become more prevalent with higher frequencies and higher component densities. Here are a few common factors to pay attention to:<\/p>\n\n\n

Route Length<\/h3>\n\n\n

At higher frequencies, the time it takes a signal to travel from the transmitting driver to receiving device matters. This is especially true for differential communications. Pulse travel time along a trace is proportional to its length. Meandering ensures that trace lengths are equal. High-speed differential lines also need to have equal electrical lengths.<\/p>\n\n\n

Clock Skewing<\/h3>\n\n\n

One consequence of uneven route lengths is clock skewing, a situation where clock edges arrive at times significantly later than the data they are clocking. Consumer products that use memory and sensor modules commonly have high-speed SPI and I2C clocks and data. In this case, you must ensure that data paths and clock paths to all ICs remain constant and within specifications.<\/p>\n\n\n

Impedance Matching<\/h3>\n\n\n

Unmatched PCB<\/a> transmission lines, which are what microstrip and striplines are, will degrade your signals. Lines need to match up to the driving circuit impedance for maximum power transfer. Common PCB microstrip and stripline impedances are around 100 \u03a9. Most radio frequency circuits and antenna feeds use 50 \u03a9. Termination resistors, which match the impedance of the line, sit at the end of a transmission line.<\/p>\n\n\n\n

Pulses reflect back to the driver if the end impedance doesn’t match or gets terminated. This would degrade your signals.<\/p>\n\n\n\n

\"electronic-pulses\"
Wikipedia: Oleg Alexandrov <\/em><\/figcaption><\/figure>\n\n\n\n

Changes in impedance along lines also result in reflections and signal degradation. Keep high-speed differential line spacing constant.<\/p>\n\n\n\n

\"high-speed-differential-routing\"
High-Speed Differential Routing<\/em><\/figcaption><\/figure>\n\n\n\n

PCB manufacturers<\/a> will create test \u201ccoupons\u201d of your PCB and Time Domain Reflectometry (TDR). Tests verify that you’ll achieve the impedances you want using the dielectric of the substrate(s) you use. Work closely with your CM \/ PCB manufacturer to ensure they produce the boards with the impedances you need.<\/p>\n\n\n

Stubs<\/h3>\n\n\n
\"electronics-stubs-illustration\"<\/figure>\n\n\n\n
\"electronics-stub-via\"
3D view of stub created from via. <\/em><\/figcaption><\/figure>\n\n\n\n

Stubs form a small transmission line, and they too can cause reflections. Try to run high-speed signals via continuous routes to minimize reflections. Stubs appear from vias that have traces that do not connect the topmost and bottom-most layers. <\/p>\n\n\n\n

They begin to matter when the frequency wavelengths begin to approach \u00bc wavelength. But remember: you need to consider the rise time of signals to determine the highest frequencies to consider. Not the base frequency of the signal. In extremely high-speed cases, via stubs may need back-drilling of vias to remove stubs.<\/p>\n\n\n

Crosstalk<\/h3>\n\n\n

During the early days of telephony, people noticed that when multiple phone conversations took place in bundled wire cables, people could hear other people\u2019s conversations. This type of signal coupling is called crosstalk. The term has stuck around. It now means any signal injected from adjacent wires.<\/p>\n\n\n\n

On two-layer boards, an easy way to reduce or eliminate crosstalk is to route signals at right angles to each other on the top and bottom layers. Keeping adjacent parallel signals well separated is another common technique that reduces crosstalk. A good rule of thumb is to keep differential pairs 8W away from other signals, where W = width of trace, and 50 mils away from clock traces.<\/p>\n\n\n\n

\"high-speed-differential-routing\"
High-Speed Differential Routing <\/em><\/figcaption><\/figure>\n\n\n\n

Using a ground plane will keep electric fields from spreading out too far and interfering with adjacent traces. <\/p>\n\n\n

Increase High-Speed PCB Performance<\/h2>\n\n\n

Maintaining good signal integrity in high-speed layouts is challenging. Follow the guidance above to greatly increase your signal quality and PCB performance. View the rest of the series here:<\/p>\n\n\n\n