{"id":1912,"date":"2017-11-13T08:00:09","date_gmt":"2017-11-13T16:00:09","guid":{"rendered":"http:\/\/www.autodesk.com\/products\/eagle\/blog\/?p=1912"},"modified":"2023-07-17T23:10:07","modified_gmt":"2023-07-18T06:10:07","slug":"avoid-signal-timing-errors-high-speed-analog-digital-conversion","status":"publish","type":"post","link":"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/avoid-signal-timing-errors-high-speed-analog-digital-conversion\/","title":{"rendered":"Everyday App Note: How to Avoid Signal Timing Errors in High-Speed Analog-to-Digital Conversion"},"content":{"rendered":"\n<p><span style=\"font-weight: 400;\">Welcome to the first installment of our Everyday App Note Series! Today\u2019s application note comes from Texas Instruments, one of the leading experts on high-speed design. They\u2019ve dug deep to uncover solutions for timing errors during high-speed Analog-to-Digital Conversion (ADC) when using Low Voltage Differential Signaling (LVDS) and a Field Programmable Gate Array (FPGA). <\/span><\/p>\n\n\n\n<figure class=\"wp-block-image aligncenter size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1024\" height=\"379\" src=\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/2023\/07\/TexasInstruments-Logo.svg_-2-1024x379.png\" alt=\"Texas Instruments\" class=\"wp-image-59573\" srcset=\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/2023\/07\/TexasInstruments-Logo.svg_-2-1024x379.png 1024w, https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/2023\/07\/TexasInstruments-Logo.svg_-2-300x111.png 300w, https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/2023\/07\/TexasInstruments-Logo.svg_-2-768x284.png 768w, https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/2023\/07\/TexasInstruments-Logo.svg_-2.png 1116w\" sizes=\"auto, (max-width: 1024px) 100vw, 1024px\" \/><\/figure>\n\n\n<h2 class=\"wp-block-heading\" id=\"who-is-this-app-note-for\">Who Is This App Note For?<\/h2>\n\n\n<p><span style=\"font-weight: 400;\">The LVDS standard does not define any connectors and protocols, which makes it easily adaptable into a variety of high-speed applications. This app note is perfect for any designer troubleshooting timing errors during high-speed analog-to-digital conversion with an LVDS data interface and an FPGA. <\/span><\/p>\n\n\n<h2 class=\"wp-block-heading\" id=\"why-should-you-read-this-app-note\">Why Should You Read This App Note?<\/h2>\n\n\n<p><span style=\"font-weight: 400;\">LVDS is one of the most popular differential signaling standards for electronics design and offers an ideal interface between an ADC and FPGA. If you\u2019re battling timing errors using single-ended signaling schemes like Complementary Metal-Oxide-Semiconductor (CMOS), then this app note is worth your time.<\/span><\/p>\n\n\n\n<figure class=\"wp-block-image aligncenter size-full wp-image-1916\"><img loading=\"lazy\" decoding=\"async\" width=\"760\" height=\"379\" src=\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/2023\/07\/Basic_LVDS_circuit_operation.png\" alt=\"lvds\" class=\"wp-image-59578\" srcset=\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/2023\/07\/Basic_LVDS_circuit_operation.png 760w, https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/2023\/07\/Basic_LVDS_circuit_operation-300x150.png 300w\" sizes=\"auto, (max-width: 760px) 100vw, 760px\" \/><figcaption class=\"wp-element-caption\"><em>This basic LVDS circuit reduces EMI thanks to the <\/em>coupling<em> of the differential pairs.<\/em><\/figcaption><\/figure>\n\n\n\n<p><span style=\"font-weight: 400;\">It\u2019s a well-known fact that differential signaling with LVDS greatly reduces noise on high-speed layouts than single-ended schemes like CMOS. By using two wires with opposite current and voltage swings in a differential signal, you get several benefits, including:<\/span><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><span style=\"font-weight: 400;\">Noise coupled onto a differential signal as common-mode is rejected by the LVDS receiver. <\/span><\/li>\n\n\n\n<li><span style=\"font-weight: 400;\">Differential signals are well known for reducing noise generation since the magnetic fields of both signals cancel each other out. <\/span><\/li>\n\n\n\n<li><span style=\"font-weight: 400;\">Current-mode drivers are not susceptible to spikes in ringing and switching which helps to reduce noise on high-speed layouts.<\/span><\/li>\n<\/ul>\n\n\n<h2 class=\"wp-block-heading\" id=\"what-problems-does-this-app-note-solve\">What Problems Does This App Note Solve?<\/h2>\n\n\n<p><span style=\"font-weight: 400;\">Data from two differential signals that aren\u2019t captured at the same time by an LVDS receiver presents signal timing and noise problems for your high-speed layout. This marginal capturing issue can only be solved with one of two methods that this app note discusses in detail:<\/span><\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li><b>Method 1<\/b><span style=\"font-weight: 400;\">. Use the ADC LVDS features to modify the delays of LVDS data lines to match an LVDS output clock.<\/span><\/li>\n\n\n\n<li><b>Method 2<\/b><span style=\"font-weight: 400;\">. Use the delay elements inside an FPGA to change the delay elements for LVDS pairs. <\/span><\/li>\n<\/ul>\n\n\n\n<p><span style=\"font-weight: 400;\">There are a lot more details inside. Learn how to avoid timing errors by <\/span><a href=\"http:\/\/www.ti.com\/lit\/an\/slaa592a\/slaa592a.pdf\"><span style=\"font-weight: 400;\">downloading this application note from Texas Instruments now! <\/span><\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Welcome to the first installment of our Everyday App Note Series! Today\u2019s application note comes from Texas Instruments, one of the leading experts on high-speed design. They\u2019ve dug deep to uncover solutions for timing errors during high-speed Analog-to-Digital Conversion (ADC) when using Low Voltage Differential Signaling (LVDS) and a Field Programmable Gate Array (FPGA). Who [&hellip;]<\/p>\n","protected":false},"author":2425,"featured_media":1913,"menu_order":0,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"inline_featured_image":false,"footnotes":""},"categories":[434],"tags":[],"coauthors":[],"class_list":["post-1912","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-eagle","dhig-theme--light"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.4 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Timing Errors in High-Speed ADC | Everyday App Note | EAGLE | Blog<\/title>\n<meta name=\"description\" content=\"Learn how to reduce noise and avoid timing errors during high-speed analog-to-digital conversion with our featured app note from Texas Instruments.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link 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