All jokes aside, there has never been a period in electronics design when ESD has been more of a problem. With ICs getting smaller every year, and devices becoming more advanced, the chance for ESD to wreak havoc on your design is a huge concern. As a designer using these devices, it\u2019s no longer just about whipping out the anti-static mats and wrist straps; now you need to double down on adding ESD protection at design time, not after. But what do you need to include? Let\u2019s find out.<\/span><\/p>\n\n\n Electrostatic Discharge (ESD) is the spontaneous and often unintended flow of electricity between two objects that have come in contact with each other. That might not be a physical contact; even close proximity will get that current jumping.<\/span><\/p>\n\n\n\n ESD isn\u2019t a new problem. In the 1400s European and Caribbean military forts were implementing safety nets to prevent ESD from blowing up their gunpowder storage. And in 1860, paper mills throughout the United States were taking advantage of steam drums, flame ionization, and grounding techniques to keep static electricity out of their paper drying process.<\/span><\/p>\n\n\n\n As you can see, ESD isn\u2019t just a problem that plagues electronics. You\u2019ll find this natural phenomenon affecting a variety of industries from petrochemical, pharmaceutical, agriculture, textiles, plastics, and a whole lot more. But closer to home in electronics design, the consequences of ESD can be catastrophic, including:<\/span><\/p>\n\n\n\n At the heart of ESD is a simple principle of electrostatic charge, which builds when two materials come into contact and separate from one another. You\u2019re probably familiar with the most common form of electrostatic charge, like when you rub your feet against the floor while wearing socks and get a shock when touching a doorknob. This process of a continuous contact\/separation between two materials all starts at the atomic level.<\/span><\/p>\n\n\n\n When two materials touch, what’s going on behind the scenes is a transfer of electrons. While atoms in a balanced state have an equal number of electrons(-) and protons(+), when these electrons begin to transfer between materials through continual and consistent contact, then everything gets out of balance. Take for example the images below; here we can see that two identical atoms that have come into contact and separated through the process of triboelectric charge. Now Material B has more electrons than Material A, and there\u2019s an imbalance to the whole equation. How will it find equilibrium?<\/span><\/p>\n\n\n\n At their core, atoms will always seek balance. And so what happens when you run your socks across the floor, collecting excess electrons in the process? Those electrons are going to find the path of least resistance in a nearby object to find equilibrium. And if that object is a metal doorknob (an excellent conductor), then you\u2019ll get a shock in the process as those electrons transfer. <\/span><\/p>\n\n\n\n The amount of charge that gets created by this triboelectric charging process has many variables to take into account, including:<\/span><\/p>\n\n\n\n You can measure the electric charge that you create between two materials in coulombs, with the following equation:<\/p>\n\n\n\n Here, <\/span>q <\/b>is the charge of an object, which is determined by multiplying its capacitance, <\/span>C<\/b>, with the voltage potential of the object, <\/span>V<\/b>. When measuring the effects of ESD on a component or circuit board, you\u2019ll commonly see ESD being described in terms of voltage or current.<\/span><\/p>\n\n\n Not all ESD is created the same. While this natural phenomenon might disrupt the workings of your components or circuit board, how it goes about doing so can be a little mysterious. Typically when you have an ESD issue, you\u2019ll find out in one of two ways:<\/span><\/p>\n\n\n This is the most obvious, where your entire circuit board or a particular component on your PCB immediately stops working. ESD will typically cause the metal to melt, oxide failure, or a junction breakdown in those ultra sensitive parts like semiconductors and integrated circuits. More often than not, catastrophic ESD failures will be found immediately when the device is tested.<\/span><\/p>\n\n\n\n Things get a little more tricky when ESD affects a circuit board or component but doesn\u2019t completely disable it. In the Latent Defect situation, an electrostatic discharge will occur, causing a part to become degraded, yet still functional. But for how much longer is the major issue. You might find yourself shipping a product or system with ESD-degraded devices, only to find them failing in the field weeks or months down the road. These are the most costly forms of ESD to fix.<\/span><\/p>\n\n\n\n Whether ESD is crippling an entire circuit board all at once, or just putting a dent in a circuit for problems down the road, there are a number of ways this damage can happen. When ESD does discharge energy, it will occur in one of three ways:<\/span><\/p>\n\n\n\n Not all electronic devices or components are sensitive to ESD, and those that can withstand the zap have a relatively high resolve for withstanding voltage spikes. However, more sensitive components like integrated circuits and microprocessors typically can only withstand 100V, and some can barely handle 10V. The smaller that package sizes, the more sensitive the device.<\/span><\/p>\n\n\n\n To stay ESD aware, here\u2019s a quick list of some of the most sensitive electronic devices in use that is susceptible to damage:<\/span><\/p>\n\n\n\n Now that you\u2019ve got a solid background on what ESD is all about let\u2019s talk about what you can do about it. It\u2019s not just about protecting yourself from ESD while tinkering with electronic devices with an anti-static mat and wrist straps. Way before you ever get a board back from your manufacturer, you need to be taking steps to add ESD protection into your design process. Let’s dive deeper:<\/span><\/p>\n\n\n\n The overall goal of designing ESD protection into your PCB is straightforward – prevent voltage levels from rising to a point where they\u2019ll start to damage your interface devices. Check out the image below. This is a typical simulated response curve for an electrostatic discharge as defined by <\/span>IEC61000-4-5<\/span><\/a>. This graph shows a peak voltage between 2,000 and 8000V, with a rise time of approximately 1ns and a peak current level at 30A.<\/span><\/p>\n\n\n\n Now, keeping these figures in mind, consider some of today\u2019s modern chipsets and integrated circuits. These devices rarely tolerate DC voltages over 3.3V, so an electrostatic discharge means immediate death for these mission-critical parts.<\/span><\/p>\n\n\n\n When you put this problem in perspective, there are a ton of variables to consider in both the circuit design<\/a> and board layout process to ensure that your device is properly protected against ESD. This problem becomes especially pronounced at the board layout level when considering the ill effects of parasitic inductance. Take for example this equation:<\/span><\/p>\n\n\n\n This will get you the voltage calculation for your parasitic inductance. Here, <\/span>Lparasitic<\/b> is the parasitic inductance of the trace, and <\/span>VLparasitic<\/b> is the voltage developed across it after a change in current over the change in time, <\/span>di\/dt<\/b>.<\/span><\/p>\n\n\n\n Using this equation, if you send an 8-kV, 30A ESD charge through a PCB trace with just 1-nH inductance, this will generate a 30V spike on a trace, but to what is that trace connected? If it\u2019s an IC, you can guarantee that component is getting fried. <\/span><\/p>\n\n\n\n We think you get the idea now, ESD is no joke! So here\u2019s what you can do about it.<\/p>\n\n\n When designing your circuit, consider adding a basic transient voltage suppressor (TVS) at your input. This protective circuit consists of two diodes and an avalanche diode, which works together to reduce the change of an ESD destroying your components. The way a TVS works is pretty simple:<\/span><\/p>\n\n\n\n Put together, this circuit will effectively \u201cclamp\u201d the voltage to within an established range, and can be approximated by the following equation:<\/span><\/p>\n\n\n\n Here, the total clamped voltage, <\/span>Vclamp<\/b>, is related to the conduction, <\/span>Vconduction<\/b>, of the type of diode being used and the dynamic resistance of the diode, <\/span>Rdynamic x current<\/b>. Keep in mind, even with this protective circuit in place using 5V DC clamp voltages and fast switching diodes; you\u2019ll still likely see ESD spikes over 100V. But the good news is that the protective circuit will limit the discharge to a shorter duration so your circuit can survive the aftermath.<\/span><\/p>\n\n\n When it comes to keeping your circuit board protected from unintended ESD attacks, keep the following tips in mind:<\/span><\/p>\n\n\n\n Always keep the traces connecting to an ESD connector as short as possible. How short? Consider this – lengthening an ESD protector trace away from its device from 200 mils to 400 mils can increase voltages by 75%. Sometimes there\u2019s nothing you can do about this, maybe the way your board layout is organized keeps an ESD device from being positioned directly on a PCB trace. But the farther away you place the ESD part from the trace, the more of a voltage spike you\u2019ll be risking.<\/span><\/p>\n\n\n\n The same holds true for ground buses. In some designs, the ESD device\u2019s ground might have to pass through vias and take a roundabout path to finally reach its ground plane. But doing this will again lead to some serious spikes in voltage, so keep those traces connecting ESD devices as short as possible.<\/span><\/p>\n\n\n\n Always take the time to review your design to ensure you have no loops on your layout. This can help significantly with ESD protection because spikes in current and voltage are easily induced in any kind of loop. Also make sure to use multiple ground planes if possible, which will help your signals to be grounded effectively and reduce the possibility of ground loops.<\/span><\/p>\n\n\n\n The closer your traces are to the edge of your board, the more likely they are to pick up electrostatic discharges. Always try to keep any sensitive traces 50 mils away from the edge of your board. Of course, input and output lines will need to find their way to the edge at some point, but these can be immediately routed away to minimize ESD dangers. However, do check with your manufacturer for their recommended clearances.<\/span><\/p>\n\n\n\n There\u2019s a good reason to keep components with shared interconnections together – the longer the traces, the more they act like antennas. Those antennas can easily receive emissions from ESD pulses. Be sure to place all of your components with shared interconnections close together, which will help to reduce antenna-like effects while also keeping your board organized.<\/span><\/p>\n\n\n\n Lastly, we always recommend keeping unprotected circuits away from the traces between a TVS circuit and its input. Doing this will allow you to minimize the exposure of sensitive components from any kind of field induction. Also be sure to place parts that are on a sensitive line closer to the center of your board to balance the parasitic inductance of your circuit.<\/span><\/p>\n\n\n\n These ESD protection tips are by no means exhaustive, and there\u2019s a ton of other strategies you can implement to keep your PCB protected. Be sure to check out this great <\/span>ESD Protection Layout Guide by Texas Instruments<\/span><\/a> for a deeper dive.<\/span><\/p>\n\n\nWhat is Electrostatic Discharge?<\/h2>\n\n\n
![\"esd-warning\"\/](\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/eagle\/2017\/07\/esd.jpg\")
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How ESD Works<\/span><\/h2>\n\n\n
![\"triboelectric-charge-contact\"\/](\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/eagle\/2017\/07\/fundamentalsP1-clip-image002.jpg\")
<\/figure>\n\n\n\n![\"triboelectric-charge-separation\"\/](\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/eagle\/2017\/07\/fundamentalsP1-clip-image004.jpg\")
<\/figure>\n\n\n\n![\"esd-static\"\/](\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/eagle\/2017\/07\/ESD_Static.jpg\")
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q = CV<\/b><\/pre>\n\n\n\n
Types of ESD<\/h2>\n\n\n
Catastrophic Failure<\/h3>\n\n\n
![\"esd-destroyed-chip\"\/](\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/eagle\/2017\/07\/ams1117_50x_lrg.jpg\")
Latent Defect<\/h3>\n\n\n
![\"latent-esd-defect\"\/](\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/eagle\/2017\/07\/esd_ic.jpg\")
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Is Your Device Susceptible to ESD?<\/h3>\n\n\n
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How to Design for ESD Protection<\/h2>\n\n\n
![\"esd-waveform\"\/](\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/eagle\/2017\/07\/4705-01_fig01.jpg\")
VL, parasitic = Lparasitic \u00d7 di\/dt<\/b><\/pre>\n\n\n\n
Circuit Design Protection<\/h3>\n\n\n
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![\"transient-voltage-suppressor-circuit\"](\"https:\/\/www.autodesk.com\/products\/fusion-360\/blog\/wp-content\/uploads\/eagle\/2017\/07\/Fig2-ESDprotect.jpg\")
Vclamp = Vconduction + (Rdynamic x current)<\/b><\/pre>\n\n\n\n
Board Layout Protection<\/h3>\n\n\n
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Don\u2019t Get Zapped<\/h2>\n\n\n