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Everyday App Note: How to Avoid Signal Timing Errors in High-Speed Analog-to-Digital Conversion

Sam Sattel


Everyday App Note: How to Avoid Signal Timing Errors in High-Speed Analog-to-Digital Conversion

Welcome to the first installment of our Everyday App Note Series! Today’s application note comes from Texas Instruments, one of the leading experts on high-speed design. They’ve dug deep to uncover solutions for timing errors during high-speed Analog-to-Digital Conversion (ADC) when using Low Voltage Differential Signaling (LVDS) and a Field Programmable Gate Array (FPGA).


Who Is This App Note For?

The LVDS standard does not define any connectors and protocols, which makes it easily adaptable into a variety of high-speed applications. This app note is perfect for any designer troubleshooting timing errors during high-speed analog-to-digital conversion with an LVDS data interface and an FPGA.

Why Should You Read This App Note?

LVDS is one of the most popular differential signaling standards for electronics design and offers an ideal interface between an ADC and FPGA. If you’re battling timing errors using single-ended signaling schemes like Complementary Metal-Oxide-Semiconductor (CMOS), then this app note is worth your time.


This basic LVDS circuit reduces EMI thanks to the coupling of the differential pairs.

It’s a well-known fact that differential signaling with LVDS greatly reduces noise on high-speed layouts than single-ended schemes like CMOS. By using two wires with opposite current and voltage swings in a differential signal, you get several benefits, including:

  • Noise coupled onto a differential signal as common-mode is rejected by the LVDS receiver.
  • Differential signals are well known for reducing noise generation since the magnetic fields of both signals cancel each other out.
  • Current-mode drivers are not susceptible to spikes in ringing and switching which helps to reduce noise on high-speed layouts.

What Problems Does This App Note Solve?

Data from two differential signals that aren’t captured at the same time by an LVDS receiver presents signal timing and noise problems for your high-speed layout. This marginal capturing issue can only be solved with one of two methods that this app note discusses in detail:

  • Method 1. Use the ADC LVDS features to modify the delays of LVDS data lines to match an LVDS output clock.
  • Method 2. Use the delay elements inside an FPGA to change the delay elements for LVDS pairs.

There are a lot more details inside. Learn how to avoid timing errors by downloading this application note from Texas Instruments now!

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